Sandy bridge, Ivy bridge, Haswell and the mess of Intel processors feature list

Written by Gionatan Danti on . Posted in Hardware analysis

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Intel CPU features

To understand why I think that Intel gas gone too far into differentiating their products, we had first to know some of them.

  • ECC (Error checking and correction): a system to detect and correct bit errors inside memory.
  • Intel64 (E64MT): Intel version of its 64-bit extensions to the classic IA32 ISA.
  • SSE4.1/4.2: a 128 bit-wide SIMD vector instruction set.
  • AVX (Advanced vector instructions): a new set of 256-bit wide vector instructions.
  • AVX2 ( Advanced vector instructions 2): the second version of the AVX instruction set, featuring FMA4-specific instructions.
  • AES-NI: specific instructions to accelerate AES encryption/decryption.
  • TXT (Trusted Execution Technology): Intel implementation of Trusted Computing.
  • TSX-NI (Transactional Synchronization Extensions): an extensions to bring transaction-like concept to main memory accesses.
  • VT-x (Virtualization Technology): provide basic virtualization infrastructure. 
  • VT-x w/EPT (extended page tables): a technology to speed up memory access from inside guest VM.
  • VT-d (Virtualization Technology for direct I/O): an advanced virtualization facility providing I/O MMU for faster guest I/O transfers.
  • ... many others

This is an incomplete list, however main features should be present (note that I purposely left out features as Turbo Boost and Hyper Thread which have a purely speed impact and don't influence intrinsic machine capabilities). I have marked bold the most important features; for the most part, these are those influencing the underlying ISA. These have an enormous importance because unless the vast majority of CPU (>90%) supports them, they will see very little (near 0) support in real life programs. The reason is simple: nobody want to write consumer-class software for a small market niche, so in order to ISA extensions to really take off they need to be readily available on almost all targeted computers.

A good example of this statement is the use of SSE2-enabled software: as SSE2 are included in the basic AMD64/Intel64 specifications (supported by nearly all CPUs around), programmers used it very extensively in the latest years, at the point that recent GCC compiler actually use the SSE2 target (largely ignoring plain-old x87 code) when compiling software for 64-bit enabled x86 processors.

To see a similar adoption for AVX code, the number of AVX processors need to dramatically increase. Any segmentation done at AVX level will badly fragment the market, leading to no AVX use in consumer programs and a stagnation of the software ecosystem around older SIMD instructions.

A similar thing can be told for the other features marked bold: if a significant slice of CPU shipments include processors with no VT-x technology, then O.S. will be very slow into adopting innovative virtualization concepts to protect kernel and user space processes (note: I'm not advocating that this must happen, but only nothing that unless nearly all processor are VT-x enabled this can not happen).

Ok, lets see how badly Intel decided to segment the market...

Comments   

 
#1 Anastasia Roupakioti 2014-04-21 17:51
Very insightful article! Absinthia Stacy
 

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